Coverart for item
The Resource VLSI-SoC: : from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers, edited by Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis

VLSI-SoC: : from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers, edited by Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis

Label
VLSI-SoC: : from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers
Title
VLSI-SoC:
Title remainder
from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers
Statement of responsibility
edited by Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis
Title variation
  • From algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers
  • 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers
Creator
Contributor
Subject
Genre
Language
eng
Summary
This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems
Member of
Dewey number
003.3
Illustrations
illustrations
Image bit depth
0
Index
no index present
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2012
http://bibfra.me/vocab/lite/meetingName
IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorDate
1975-,
http://library.link/vocab/relatedWorkOrContributorName
  • Burg, Andreas
  • Coṣkun, Ayṣe
  • Guthaus, Matthew
  • Katkoori, Srinivas
  • Reis, Ricardo A. L.
Series statement
IFIP Advances in Information and Communication Technology,
Series volume
418
http://library.link/vocab/subjectName
  • Integrated circuits
  • Systems on a chip
  • Computer science
  • Computer hardware
  • Computer network architectures
  • Computer Science
  • Computer System Implementation
  • Computer Systems Organization and Communication Networks
Label
VLSI-SoC: : from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers, edited by Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis
Instantiates
Publication
Copyright
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Color
not applicable
Contents
FPGA-Based High-Speed Authenticated Encryption System -- A Smart Memory Accelerated Computed Tomography Parallel Backprojection -- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure -- Spatially-Varying Image Warping: Evaluations and VLSI Implementations -- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing -- Configurable Low-Latency Interconnect for Multi-core Clusters -- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks -- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections -- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture -- CMOS Implementation of Threshold Gates with Hysteresis -- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates
Control code
ocn868040953
Dimensions
unknown
Extent
1 online resource (x, 233 pages)
File format
multiple file formats
Form of item
online
Isbn
9783642450730
Isbn Type
(electronic bk.)
Level of compression
uncompressed
Other control number
10.1007/978-3-642-45073-0
Other physical details
illustrations
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(OCoLC)868040953
Label
VLSI-SoC: : from algorithms to circuits and system-on-chip design : 20th IFIP WG 10.5/IEEE international conference on very large scale integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, revised selected papers, edited by Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis
Publication
Copyright
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Color
not applicable
Contents
FPGA-Based High-Speed Authenticated Encryption System -- A Smart Memory Accelerated Computed Tomography Parallel Backprojection -- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure -- Spatially-Varying Image Warping: Evaluations and VLSI Implementations -- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing -- Configurable Low-Latency Interconnect for Multi-core Clusters -- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks -- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections -- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture -- CMOS Implementation of Threshold Gates with Hysteresis -- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates
Control code
ocn868040953
Dimensions
unknown
Extent
1 online resource (x, 233 pages)
File format
multiple file formats
Form of item
online
Isbn
9783642450730
Isbn Type
(electronic bk.)
Level of compression
uncompressed
Other control number
10.1007/978-3-642-45073-0
Other physical details
illustrations
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(OCoLC)868040953

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