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The Resource Design recipes for FPGAs using Verilog and VHDL, Peter Wilson

Design recipes for FPGAs using Verilog and VHDL, Peter Wilson

Label
Design recipes for FPGAs using Verilog and VHDL
Title
Design recipes for FPGAs using Verilog and VHDL
Statement of responsibility
Peter Wilson
Creator
Subject
Language
eng
Summary
This book provides a collection of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy-to-grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create "real world" designs that fit the device required and which are fast and reliable to implement -- Book jacket
Cataloging source
PU
http://library.link/vocab/creatorDate
1939-
http://library.link/vocab/creatorName
Wilson, Peter R.
Illustrations
illustrations
Index
index present
Literary form
non fiction
Nature of contents
bibliography
http://library.link/vocab/subjectName
  • Field programmable gate arrays
  • Verilog (Computer hardware description language)
  • VHDL (Computer hardware description language)
Target audience
specialized
Label
Design recipes for FPGAs using Verilog and VHDL, Peter Wilson
Instantiates
Publication
Copyright
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier MARC source
rdacarrier
Content category
text
Content type MARC source
rdacontent
Contents
Introduction. Overview ; verilog vs. VHDL ; Why FPGAs? ' Summary -- An FPGA primer. Introduction ; FPGA evolution ; Programmable logic devices ; Field programmable gate arrays ; FPGA design techniques ; Design constraints using FPGAs ; Development kits and boards ; Summary -- A VHDL primer : the esssentials. Introduction ; Entity: model interface ; Architecture: model behavior ; Process: basic functional unit in VDHL ; Basic variable types and operators ; Decisions and loops ; Hierarchical design ; Debugging models ; Basic data types ; Summary -- A Verilog primer : the essentials. Introduction ; Modules ; Connections ; Wires and registers ; Defining the module behavior ; Parameters ; Variables ; Data types ; Decision making ; Loops ; Summary -- Design automation of FPGAs. Introduction ; Simulation ; Libraries ; std_logic type definition ; Synthesis ; RTL design flow ; Physical design flow ; Place and route ; Timing analysis ; Design pitfalls ; Summary -- Synthesis. Introduction ; Numeric types ; Wait statements ; Assertions ; Loops ; Some interesting cases where synthesis may fail ; What is being synthesized? ; Summary -- High speed video application. Introduction ; The camera link interface ; Getting started ; Specifying the interfaces ; Defining the top level design ; System block definitions and interfaces ; The camera link interface ; The PC interface ; Summary -- Simple embedded processors. Introduction ; A simple embedded processor ; A simple embedded processor implemented in VHDL ; A simple embedded processor implemented in Verilog ; Soft core processors on an FPGA ; Summary -- Digital filters. Introduction ; Converting S domain to Z domain ; Implementing Z domain functions in VHDL ; Finite impulse response filters ; Infinite impulse response filters ; Summary -- Secure systems. Introduction to block cyphers ; Feistel lattice structures ; The data encryption standard (DES) ; Advanced encryption standard ; Summary -- Memory. Introduction ; Modeling memory in HDLs ; Read only memory ; Random access memory ; Synchronous RAM ; Flash memory ; Summary -- PS/2 mouse interface. Introduction ; PS/2 mouse basics ; PS/2 mouse commands ; PS/2 mouse data packets ; PS/2 operation modes ; PS/2 mouse with wheel ; Basic PS/2 mouse handler VHDL ; Modified PS/2 mouse handler VHDL ; Basic PS/2 mouse handler in Verilog ; Summary -- PS/2 keyboard interface. Introduction ; PS/2 keyboard basics ; PS/2 keyboard commands ; PS/2 keyboard data packets ; PS/2 keyboard operation modes ; Summary -- A simple VGA interface. Introduction ; Basic pixel timing ; Image handling ; A VGA interface in VHDL ; A VGA interface in Verilog ; Summary -- Serial communications. Introduction ; Manchester encoding and decoding ; Implementing the Manchester encoding scheme using VHDL ; Implementing the Manchester encoding scheme using Verilog ; NRZ (Non-return-to-zero) coding and decoding ; RS-232 ; Universal Serial Bus ; Summary -- Design optimization. Introduction ; Techniques for logic optimization ; Improving performance ; Critical path analysis ; Summary -- Behavioral modeling in using HDLs. Introduction ; How to go from RTL to behavioral HDL descriptions ; Implementing the behavioral model using VHDL ; Implementing the behavioral model using Verilog ; Summary -- Mixed signal modeling. Introduction ; Basic modeling approach for VHDL-AMS ; Introduction to VHDL-AMS ; VHDL-AMS analog pins: TERMINALS ; Mixed domain modeling ; VHDL-AMS analog variables: quantities ; Simultaneous equations in VHDL-AMS ; A VHDL-AMS example: A DC voltage source ; A VHDL-AMS example: resistor ; Differential equations in VHDL-AMS ; Mixed-signal modeling with VHDL-AMS ; A basic switch model ; Basic VHDL-AMS comparator model ; Multiple domain modeling ; Introduction to Verilog-AMS ; Verilog-AMS: analog ports ; Mixed domain modeling in Verilog-AMS ; Verilog-AMS analog variables ; Verilog-AMS analog equations ; A Verilog-AMS example ; Differential equations in Verilog-AMS ; Mixed signal modeling in Verilog-AMS ; Multiple domain modeling using Verilog-AMS ; Summary -- Design optimization example: DES. Introduction ; The data encryption standard ; MOODS ; Initial design ; Initial synthesis ; Optimizing the data path ; Final optimization ; Results ; Tripe DES ; Comparing the approaches ; Summary -- Latches, flip-flops, and registers. Introduction ; Latches ; Flip-flops ; Registers ; Summary -- ALU functions. Introduction ; Logic functions in VHDL ; Structural n-bit addition ; Logic functions in Verilog ; Configurable n-bit addition ; Two's complement ; Summary -- Finite state machines in VHDL and verilog. Introduction ; State transition diagrams ; Implementing finite state machines in VHDL ; Implementing finite state machines in Verilog ; Testing the finite state machine model ; Summary -- Fixed point arithmetic. Introduction ; Basic fixed point types in VDHL ; Fixed point functions in VHDL ; Testing the VHDL fixed point functions ; Fixed point types in Verilog ; Floating point types in Verilog ; Summary -- Counters. Introduction ; Basic binary counter using VHDL ; Basic binary counter using Verilog ; Synthesized simple binary counter ; Shift register ; The Johnson counter ; BCD counter ; Summary -- Decoders and multiplexers. Decoders ; Multiplexers ; Summary -- Multiplication. Introduction ; Basic binary multiplication ; Basic binary counter usingHDL unsigned multiplier ; Synthesis of the multiplication function ; Simple multiplication using VDHL ; Simple multiplication using Verilog ; Summary -- Simple 7-segment (LCD) displays. Introduction ; VDHL LCD module decoder ; Verilog LCD module decoder ; Summary
Control code
16133610
Dimensions
24cm
Edition
Second edition
Extent
xix, 369 pages
Isbn
9780080971292
Isbn Type
(paperback)
Media category
unmediated
Media MARC source
rdamedia
Other physical details
illustrations
Label
Design recipes for FPGAs using Verilog and VHDL, Peter Wilson
Publication
Copyright
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier MARC source
rdacarrier
Content category
text
Content type MARC source
rdacontent
Contents
Introduction. Overview ; verilog vs. VHDL ; Why FPGAs? ' Summary -- An FPGA primer. Introduction ; FPGA evolution ; Programmable logic devices ; Field programmable gate arrays ; FPGA design techniques ; Design constraints using FPGAs ; Development kits and boards ; Summary -- A VHDL primer : the esssentials. Introduction ; Entity: model interface ; Architecture: model behavior ; Process: basic functional unit in VDHL ; Basic variable types and operators ; Decisions and loops ; Hierarchical design ; Debugging models ; Basic data types ; Summary -- A Verilog primer : the essentials. Introduction ; Modules ; Connections ; Wires and registers ; Defining the module behavior ; Parameters ; Variables ; Data types ; Decision making ; Loops ; Summary -- Design automation of FPGAs. Introduction ; Simulation ; Libraries ; std_logic type definition ; Synthesis ; RTL design flow ; Physical design flow ; Place and route ; Timing analysis ; Design pitfalls ; Summary -- Synthesis. Introduction ; Numeric types ; Wait statements ; Assertions ; Loops ; Some interesting cases where synthesis may fail ; What is being synthesized? ; Summary -- High speed video application. Introduction ; The camera link interface ; Getting started ; Specifying the interfaces ; Defining the top level design ; System block definitions and interfaces ; The camera link interface ; The PC interface ; Summary -- Simple embedded processors. Introduction ; A simple embedded processor ; A simple embedded processor implemented in VHDL ; A simple embedded processor implemented in Verilog ; Soft core processors on an FPGA ; Summary -- Digital filters. Introduction ; Converting S domain to Z domain ; Implementing Z domain functions in VHDL ; Finite impulse response filters ; Infinite impulse response filters ; Summary -- Secure systems. Introduction to block cyphers ; Feistel lattice structures ; The data encryption standard (DES) ; Advanced encryption standard ; Summary -- Memory. Introduction ; Modeling memory in HDLs ; Read only memory ; Random access memory ; Synchronous RAM ; Flash memory ; Summary -- PS/2 mouse interface. Introduction ; PS/2 mouse basics ; PS/2 mouse commands ; PS/2 mouse data packets ; PS/2 operation modes ; PS/2 mouse with wheel ; Basic PS/2 mouse handler VHDL ; Modified PS/2 mouse handler VHDL ; Basic PS/2 mouse handler in Verilog ; Summary -- PS/2 keyboard interface. Introduction ; PS/2 keyboard basics ; PS/2 keyboard commands ; PS/2 keyboard data packets ; PS/2 keyboard operation modes ; Summary -- A simple VGA interface. Introduction ; Basic pixel timing ; Image handling ; A VGA interface in VHDL ; A VGA interface in Verilog ; Summary -- Serial communications. Introduction ; Manchester encoding and decoding ; Implementing the Manchester encoding scheme using VHDL ; Implementing the Manchester encoding scheme using Verilog ; NRZ (Non-return-to-zero) coding and decoding ; RS-232 ; Universal Serial Bus ; Summary -- Design optimization. Introduction ; Techniques for logic optimization ; Improving performance ; Critical path analysis ; Summary -- Behavioral modeling in using HDLs. Introduction ; How to go from RTL to behavioral HDL descriptions ; Implementing the behavioral model using VHDL ; Implementing the behavioral model using Verilog ; Summary -- Mixed signal modeling. Introduction ; Basic modeling approach for VHDL-AMS ; Introduction to VHDL-AMS ; VHDL-AMS analog pins: TERMINALS ; Mixed domain modeling ; VHDL-AMS analog variables: quantities ; Simultaneous equations in VHDL-AMS ; A VHDL-AMS example: A DC voltage source ; A VHDL-AMS example: resistor ; Differential equations in VHDL-AMS ; Mixed-signal modeling with VHDL-AMS ; A basic switch model ; Basic VHDL-AMS comparator model ; Multiple domain modeling ; Introduction to Verilog-AMS ; Verilog-AMS: analog ports ; Mixed domain modeling in Verilog-AMS ; Verilog-AMS analog variables ; Verilog-AMS analog equations ; A Verilog-AMS example ; Differential equations in Verilog-AMS ; Mixed signal modeling in Verilog-AMS ; Multiple domain modeling using Verilog-AMS ; Summary -- Design optimization example: DES. Introduction ; The data encryption standard ; MOODS ; Initial design ; Initial synthesis ; Optimizing the data path ; Final optimization ; Results ; Tripe DES ; Comparing the approaches ; Summary -- Latches, flip-flops, and registers. Introduction ; Latches ; Flip-flops ; Registers ; Summary -- ALU functions. Introduction ; Logic functions in VHDL ; Structural n-bit addition ; Logic functions in Verilog ; Configurable n-bit addition ; Two's complement ; Summary -- Finite state machines in VHDL and verilog. Introduction ; State transition diagrams ; Implementing finite state machines in VHDL ; Implementing finite state machines in Verilog ; Testing the finite state machine model ; Summary -- Fixed point arithmetic. Introduction ; Basic fixed point types in VDHL ; Fixed point functions in VHDL ; Testing the VHDL fixed point functions ; Fixed point types in Verilog ; Floating point types in Verilog ; Summary -- Counters. Introduction ; Basic binary counter using VHDL ; Basic binary counter using Verilog ; Synthesized simple binary counter ; Shift register ; The Johnson counter ; BCD counter ; Summary -- Decoders and multiplexers. Decoders ; Multiplexers ; Summary -- Multiplication. Introduction ; Basic binary multiplication ; Basic binary counter usingHDL unsigned multiplier ; Synthesis of the multiplication function ; Simple multiplication using VDHL ; Simple multiplication using Verilog ; Summary -- Simple 7-segment (LCD) displays. Introduction ; VDHL LCD module decoder ; Verilog LCD module decoder ; Summary
Control code
16133610
Dimensions
24cm
Edition
Second edition
Extent
xix, 369 pages
Isbn
9780080971292
Isbn Type
(paperback)
Media category
unmediated
Media MARC source
rdamedia
Other physical details
illustrations

Library Locations

    • Manawatū LibraryBorrow it
      Tennent Drive, Palmerston North, Palmerston North, 4472, NZ
      -40.385340 175.617349
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